1. Field of the Invention
The present invention generally relates to a semiconductor integrated circuit and a manufacturing method thereof, and particularly to a semiconductor integrated circuit including a conductive plug in a contact hole formed in an insulating film provided on a substrate and a manufacturing method thereof.
2. Description of the Background Art
With the increased level of integrated of a semiconductor integrated circuit, the width of an interconnection wiring and the size of a contact hole have been reduced. A method has been known for connecting a lower interconnection layer or a semiconductor substrate to an upper interconnection layer via a contact hole, wherein a metal film is formed in the contact hole by sputtering. However, it is difficult to form such a metal film in a fine contact hole with a sufficient coverage by sputtering. For a semiconductor integrated circuit including a fine contact hole, therefore, a plug technique has been generally used in which a high melting point metal film made from tungsten (W) or the like is formed in a wide region containing the contact hole by CVD and then a metal film is selectively formed in the contact hole by etching-back.
A related art method of manufacturing a semiconductor integrated circuit using the above plug technique will be described below with reference to FIGS. 10 to 16. In these figures, like or corresponding parts are designated by like reference numerals and explanation thereof is omitted.
In accordance with the related art manufacturing method, as shown in FIG. 10, oxide isolation regions 2, a gate electrode 3 and source/drain regions 4 of each transistor, and a first interlayer insulating film 5 are formed in or on a semiconductor substrate 1. A first contact hole 6 communicated to one source/drain region 4 is formed in the first interlayer insulating film 5. A metal film is formed on the surface of the first interlayer insulating film 5 in such a manner as to fill the first contact hole 6. The metal film is then patterned by photolithography and etching, to form a first interconnection layer 7.
Referring to FIG. 11, a second interlayer insulating film 8 is formed in such a manner as to cover the first interconnection layer 7. A second contact hole 9 is formed in such a manner as to be opened to the other source/drain region 4 through the second interlayer insulating film 8. A polysilicon layer is formed over the entire surface of the semiconductor substrate 1, and patterned by photolithography and etching to form a charge storage node 10 (hereinafter, referred to as xe2x80x9cstorage node 10xe2x80x9d).
A third insulating film 11 is thinly formed in such a manner as to cover the storage node 10. Then, a polysilicon layer is formed again on the third insulating film 11. The polysilicon layer is patterned by photolithography and etching, to form an upper electrode 12 for storage of charges (hereinafter, referred to as xe2x80x9ccell plate 12xe2x80x9d). The storage node 10, the third insulating film 11, and the cell plate 12 constitute a capacitor functioning as a memory cell.
The amount of charges allowed to be stored in the capacitor is proportional to the surface area of the storage node 10, and inversely proportional to the thickness of the third insulating film 11. As the device structure becomes finer, the area on the substrate which is allocated to the storage node 10 becomes smaller. Accordingly, in general, to ensure the necessary charges allowed to be stored in the capacitor, the thickness of the third insulating film 11 is made thin and the height of the storage node 10 is made large.
Referring to FIG. 12, a fourth interlayer insulating film 13 and a fifth interlayer insulating film 14 are sequentially formed over the entire surface of the semiconductor substrate 1 in such a manner as to cover the cell plate 12. The first, second, fourth and fifth interlayer insulating films 5, 8, 13 and 14 are selectively removed by photolithography and etching, to form a third contact hole 15 which is opened through the above films to the source/drain region 4 of a transistor separated from the above transistor by the oxide isolation region 2.
The region on the semiconductor substrate 1 is separated into a capacitor region in which the capacitor is to be formed (hereinafter, referred to as xe2x80x9cmemory cell regionxe2x80x9d) and a peripheral circuit region in which a peripheral circuit is to be formed. A surface stepped portion stemming from the storage node 10 is formed between the memory cell region and the peripheral circuit region. If the surface stepped portion is larger than the focal depth upon photolithography, a failure in resolution of a resist pattern may easily occur. Also upon etching of high melting point metal films to be described later, as the surface stepped portion becomes larger, an etching residue remains easier on the stepped portion, leading to an electric short-circuit failure. Further, as the height of the storage node 10 becomes larger, the problem due to the surface stepped portion becomes more serious.
To suppress occurrence of the above-described problem, the fourth interlayer insulating film 13 is usually configured as a BPSG (Boro-Phospho Silicate Glass) film. BPSG film has a property that being softened and planarized at a high temperature of 800xc2x0 C. or more to make the surface thereof into a smooth flow shape. The use of the BPSG film as the interlayer insulating film is effective to easily suppress the surface stepped portion of the device. The planarization characteristic of the BPSG film is dependent on the concentrations of boron (B) and phosphorus (P). To be more specific, as the concentrations of B and P become higher, the planarization characteristic of the BPSG film becomes more desirable.
The quality of the BPSG film containing B and P at high concentrations is generally unstable, and more specifically, it is liable to be changed depending on moisture absorption and the like. Further, since the BPSG film is poor in adhesion with a resist used for photolithography, there occurs a problem that when a resist pattern is directly formed on the BPSG film, the resist pattern may be peeled therefrom. For this reason, as described above, the insulating film having the double layer structure of the fourth interlayer insulating film (BPSG film) 13 for ensuring planarization between the memory cell region and the peripheral circuit region and the fifth interlayer insulating film 14 formed on the fourth interlayer insulating film 13 to a thickness ranging from several tens to several hundreds nm is provided on the cell plate 12.
After removal of the resist pattern used as a mask upon selective etching for forming the third contact hole 15, the semiconductor substrate 1 is generally subjected to wet cleaning using a NH4OH/H2O2 solution or the like for removing foreign matters remaining on the wafer surface. At this time, the surface of the fifth interlayer insulating film 14 is etched to about several tens nm and also a portion, exposed as the inner wall of the third contact hole 15, of the fourth interlayer insulating film 13 is etched.
Upon etching using the NH4OH/H2O2 solution for wet cleaning, the etching rate for the fourth interlayer insulating film 13 containing B and P is larger than that for the fifth interlayer insulating film 14. Accordingly, by the above-described wet cleaning, irregularities shown in FIG. 12 are formed on the inner wall of the third contact hole 15. The irregularities formed on the inner wall of the contact hole 15 can be somewhat suppressed by shortening the cleaning time; however, if the cleaning time is shortened, there occurs a problem in degrading the effect of removing foreign matters thereby reducing the manufacturing yield.
Referring to FIG. 13, a first high melting point metal film 16 is formed by sputtering or the like in such a manner as to cover the inner wall of the third contact hole 15 and the surface of the fifth interlayer insulating film 14. Then a second high melting point metal film 17 is formed on the first high melting point metal film 16 by CVD or the like. The first and second high melting point metal films 16 and 17 deposited on the fifth interlayer insulating film 14 are removed by RIE (Reactive Ion Etching) to form a metal plug 18 composed of the first and second high melting point metal films 16 and 17 only in the third contact hole 15. Each of the first and second high melting point metal films 16 and 17 may be made from titanium (Ti) or W, or a nitride or silicate thereof.
FIGS. 14 and 15 are views each showing, on a large scale, an opening end portion of the third contact hole 15. Specifically, FIG. 14 shows a state in which the first and second high melting point metal films 16 and 17 remain on the fifth interlayer insulating film 14. FIG. 15 shows a state after the first and second high melting point metal films 16 and 17 are removed from the fifth interlayer insulating film 14.
As shown in FIG. 14, at the opening end portion of the third contact hole 15, a diameter of the opening formed in the fourth interlayer insulating film 13 is larger than a diameter (2t1) of the opening formed in the fifth interlayer insulating film 14. In other words, at the opening end portion of the third contact hole 15, the fifth interlayer insulating film 14 is protruded from the wall surface of the fourth interlayer insulating film 13 by a specific length. In the case where the first high melting point metal film 16 is formed by sputtering under such a situation, since the formation of the metal film is blocked right under the fifth interlayer insulating film 14, a portion near the upper end of the fourth interlayer insulating film 13 is not covered with the first high melting point metal film 16.
When there exist the portion not covered with the first high melting point metal film 16 on the inner wall of the third contact hole 15 as well as the portion covered therewith, a local stress is liable to be applied to the second high melting point metal film 17 which is formed on the above portions. As a result, if the portion not covered with the first high melting point metal film 16 is present, the second high melting point metal film 17 may be easily peeled due to the above-described local stress. This causes a problem in degrading the yield of the device.
Further, upon formation of the second high melting point metal film 17 under the condition shown in FIG. 14, when the thickness of the second high melting point metal film 17 reaches the value t1, the opening end portion of the third contact hole 15 is blocked. This causes a problem that although the second high melting point metal film 17 can be formed on the flat portion on the substrate to a normal thickness t17 ( greater than t1), it cannot be formed on the inner wall of the contact hole 15 to a thickness of t1 or more. In this case, a cavity remains in the third contact hole 15 at a position right under the protruded portion of the fifth interlayer insulating film 14.
As shown in FIG. 15, the cavity remaining in the third contact hole 15 is exposed by etched-back the second high melting point metal film 17 and thereby formed a depressing (called xe2x80x9ca recessxe2x80x9d and assumed the thickness to be xe2x80x9chxe2x80x9d hereunder) at the upper end of the third contact hole 15. During a removal of the first and second high melting point metal films 16 and 17, the necessary over-etch amount becomes larger as the planarization of the wafer is poorer. Accordingly, as the planarization of the wafer mainly depending on the planarization of the fourth interlayer insulating film 13 is poorer, the depth xe2x80x9chxe2x80x9d of the recess becomes larger, with a result that the cavity in the contact hole is easier to be exposed.
Referring to FIG. 16, a metal film 19 is formed in such a manner as to cover the fifth interlayer insulating film 14 and the metal plug 18. The metal film 19 is usually made from an aluminum alloy such as AlSi, AlSiCu or AlCu. Such an aluminum alloy having a high reflectance is easy to cause halation upon photolithography, and therefore, an anti-reflection film 20 is formed on the metal film 19. The anti-reflection film 20 is generally made from a high melting point metal such as TiW, WSi, MoSi, TiW or W, or a compound thereof. The anti-reflection film 20 plays a role of not only reducing the reflectance of the surface of the metal film 19 but also reinforcing the mechanical strength of the metal film 19 thereby enhancing the reliability of the device.
The metal film 19 and the anti-reflection film 20 are patterned by photolithography and etching, to form a second interconnection layer 21. After formation of the second interconnection layer 21, the semiconductor substrate is subjected to cleaning treatment using a solvent containing ammonium fluoride or an amine based solvent.
Since the metal film 19 is not formed on the cavity portion of the metal plug 18, the cavity portion is left exposed after the second interconnection layer 21 is formed. As a result, the solvent used for the above cleaning treatment deeply permeates in the metal plug 18. If the solvent is not sufficiently cleaned and remains in the metal plug 18, the second high melting point metal film 17 and the metal film 19 may be corroded by the solvent. With progress of such corrosion, an electrical open failure may occur, giving rise to a problem that the semiconductor integrated circuit is not normally operated.
As described above, the conventional semiconductor integrated circuit has disadvantages in degrading the yield resulting from the irregularities formed on the inner wall of the contact hole, that is, degrading the yield by peeling of the film upon formation of the metal plug, and causing an electrical open failure resulting from formation of a cavity in the metal plug.
A method including a step for carrying out CMP (Chemical Mechanical Polishing) after formation of a conductive layer has been known as a method for forming a metal plug in a contact hole, as illustratively disclosed in Japanese Patent Laid-open Nos. Hei 7-288244 and Hei 9-167797. The method of forming a metal plug by using CMP can reduce the size of the above-described recess, thereby avoiding the above problems caused upon formation of a metal plug by using RIE.
To carry out CMP in manufacture of a semiconductor integrated circuit, however, it is required to newly prepare a polishing apparatus for CMP and a cleaning apparatus for cleaning a wafer after polishing. Also, to form a metal plug by CMP, the surface of an insulating film in which a contact hole is to be formed must be previously planarized, thereby causing a problem that the manufacturing process is complicated.
The present invention has been conceived to solve the previously-mentioned problems, and a general object of the present invention is to provide a novel and useful semiconductor integrated device and a manufacturing method thereof.
A more specific object of the present invention is to provide a semiconductor integrated circuit which can be manufactured without the necessity of a new manufacturing apparatus and also without complication of the manufacturing process, and which allows a metal plug to be formed without occurrence of peeling of a metal film; and a manufacturing method thereof.
A second object of the present invention is to provide a semiconductor integrated circuit which can be manufactured without the necessity of a new manufacturing apparatus and also without complication of the manufacturing process, and which can prevent occurrence of an electrical open failure resulting from exposure of a cavity in a metal plug, thereby keeping electrically stable characteristics; and a manufacturing method thereof.
The above objects of the present invention are achieved by a semiconductor integrated circuit having an interconnection structure including a conductive plug passing through insulating films on a substrate. The circuit includes a first insulating film. On the first insulating film is provided a second insulating film. A contact hole is provided so as to pass through the first and second insulating films. A conductive plug is provided in the contact hole. An interconnection layer is provided on the second insulating film in such a manner as to be conducted to the conductive plug. A recess is provided at the upper end surface of the conductive plug contained in the contact hole. The recess depresses the upper end surface of the conductive plug to a position lower than the upper surface of the second insulating film. The thickness of the second insulating film is larger than the depth of said recess.
Above objects of the present invention are also achieved by a semiconductor integrated circuit having an interconnection structure including a conductive plug passing through insulating films on a substrate. The circuit includes a first insulating film. On the first insulating film is provided a second insulating film. A contact hole is provided in such a manner as to pass through the first and second insulating films. A conductive plug is provided in the contact hole. An interconnection layer is provided on the second insulating film in such a manner as to be conducted to the conductive plug. The contact hole is provided in such a manner that the opening diameter of a portion near the opening end of the contact hole becomes larger as nearing the opening end.
Above objects of the present invention are further achieved by a method of manufacturing a semiconductor integrated circuit. The method includes a step of forming a second insulating film on a first insulating film. A contact hole is formed so as to pass through the first and second insulating films. The surface of the second insulating film is etching-back after formation of the contact hole. A conductive film is formed on the inner surface of the contact hole and the surface of the second insulating film after completion of the etching-back. The conductive film is etched-back until the second insulating film is exposed to form a conductive plug in the contact hole. An interconnection layer is formed on the second insulating film in such a manner that the interconnection layer is conducted to the conductive plug.